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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion mcp data sheet tm
ds05-50222-1e fujitsu semiconductor data sheet stacked mcp (multi-chip package) flash memory & sram cmos 64m ( 16) flash memory & 8m ( 16) sram mb84sd23280fa/mb84sd23280fe -70 n n n n features ? power supply voltage of 1.65 v to 1.95 v ? high performance 70 ns maximum access time (flash) 70 ns maximum access time (sram) ? operating temperature C30 c to +85 c ? package 73-ball fbga (continued) n n n n product lineup *: both v cc f and v cc s must be in recommended operation range when either part is being accessed. n n n n pac k ag e flash memory sram supply voltage (v) v cc f* = 1.8 v v cc s* = 1.8 v max address access time (ns) 70 70 max ce access time (ns) 70 70 max oe access time (ns) 20 35 73-ball plastic fbga (bga-73p-m03) +0.15v C0.15 v +0.15v C0.15 v
mb84sd23280fa/mb84sd23280fe -70 2 (continued) flash memory ?0.17 m m m m m process technology ? simultaneous read/write operation (dual bank) ? flexbank tm * 1 bank a: 16m bit (16kb 4 and 64kb 31) bank b: 16m bit (64kb 32) bank c: 16m bit (64kb 32) bank d: 16m bit (16kb 4 and 64kb 31) ? minimum 100,000 program/erase cycles ? sector erase architecture four 8k words, a hundred twenty-eight 32k words sectors. any combination of sectors can be concurrently erased. also supports full chip erase. ?wp input pin at v il , allows protection of all sectors, regardless of sector protection/unprotection status at v ih , allows removal of sector protection ? embedded erase tm * 2 algorithms automatically preprograms and erases the chip or any sector ? embedded program tm * 2 algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? automatic sleep mode when address remain stable, the device automatically switches itself to low power mode ?low v cc write inhibit ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device resumes the erase operation ? sector protection software command sector locking ? please refer to mbm29bs64lf datasheet in detailed function sram ? power dissipation operating : 50 ma max standby :15 m a max ? power down features using ce 1s and ce2s ? data retention supply voltage: 1.0 v to 1.95 v ?ce 1s and ce2s chip select ? byte data control: lb (dq 7 to dq 0 ), ub (dq 15 to dq 8 ) *1: flexbank tm is a trademark of fujitsu limited, japan. *2: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mb84sd23280fa/mb84sd23280fe -70 3 n n n n pin assignment fbga (top view) marking side (bga-73p-m03) e7 a13 e6 a9 e5 a20 e4 rdy e3 a18 e2 a5 a2 e8 a21 g7 n.c. dq6 g3 dq1 g2 vss g1 a0 g8 a16 h7 dq15 h6 dq13 h5 dq4 h4 dq3 h3 dq9 h2 oe cef h8 n.c. f7 a14 a10 f3 a17 f2 a4 f1 a1 f8 n.c. j7 dq7 j6 dq12 j5 vccs j4 vccf j3 dq10 j2 dq0 ce1s j8 vss k7 dq14 k6 dq5 k5 n.c. k4 dq11 k3 dq2 dq8 d7 a12 d6 a19 d5 ce2s d4 reset d3 ub d2 b1 a6 a7 a3 d8 a15 c7 a11 c6 a8 c5 we c4 wp c3 lb g4 f4 c1 c8 n.c. n.c. l1 k8 e9 g9 n.c. h9 f9 n.c. j9 d9 n.c. n.c. n.c. n.c. n.c. n.c. b6 b5 g10 f10 n.c. n.c. n.c. b10 a10 m1 n.c. m10 n.c. n.c. n.c. a1 l10 l6 l5
mb84sd23280fa/mb84sd23280fe -70 4 n n n n pin description pin configuration n n n n block diagram pin name function input/output a 18 to a 0 address inputs (common) i a 21 , a 20 , a 19 address inputs (flash) i dq 15 to dq 0 data inputs/outputs (common) i/o ce f chip enable (flash) i ce 1s chip enable (sram) i ce2s chip enable (sram) i oe output enable (common) i we write enable (common) i rdy ready outputs (flash) open drain output o ub upper byte control (sram) i lb lower byte control (sram) i reset hardware reset pin (flash) i wp write protect (flash) i n.c. no internal connection ? v ss device ground (common) power v cc f device power supply (flash) power v cc s device power supply (sram) power v ss v cc s 64 m bit reset flash memory we 8 m bit sram ce f a 21 to a 0 oe ce 1s v ss v cc f a 21 to a 0 a 18 to a 0 dq 15 to dq 0 rdy lb ub wp ce2s dq 15 to dq 0 dq 15 to dq 0
mb84sd23280fa/mb84sd23280fe -70 5 n nn n device bus operations user bus operations legend : l = v i l , h = v i h , x = v i l or v i h . see n dc c h a ra c te ri s t i c s for voltage levels. *1: other operations except for this indicated table are prohibited. *2: do not apply ce f = v il , ce 1s = v il and ce2s = v ih all at once. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: at wp =v il , all sectors are protected. operation* 1, * 3 ce fce 1s ce2s oe we lb ub dq 7 to dq 0 dq 15 to dq 8 reset wp * 4 full standby h hx x x x x high-z high-z h x xl output disable hl h h h x x high-z high-z hx x x h h high-z high-z l hx h h x x high-z high-z xl read from flash* 2 l hx lhxx d out d out hx xl write to flash l hx hlxx d in d in hh xl read from sram h l h l h ll d out d out hx hl high-z d out lh d out high-z write to sram h l h x l ll d in d in hx hl high-z d in lh d in high-z flash all sector write protection* 4 xx xxxxx x x h l flash hardware reset x hx x x x x high-z high-z l x xl
mb84sd23280fa/mb84sd23280fe -70 6 n n n n absolute maximum ratings * : minimum dc voltage on input or l/o pins are C0.5 v. during voltage transitions, inputs may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input and l/o pins are v cc +0.5 v. during voltage transitions, outputs may positive overshoot to v cc +2.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 40 + 125 c ambient temperature with power applied t a - 30 + 85 c voltage with respect to ground all pins * v in - 0.3 v cc f + 0.1 v v out - 0.3 v cc s + 0.1 v v cc f supply * v cc f - 0.2 + 2.5 v v cc s supply * v cc s - 0.5 + 2.5 v parameter symbol value unit min max ambient temperature t a - 30 + 85 c v cc f supply voltages v cc f + 1.65 + 1.95 v v cc s supply voltages v cc s + 1.65 + 1.95 v
mb84sd23280fa/mb84sd23280fe -70 7 n n n n dc characteristics * 1, * 2 *1 : all voltage are referenced to v ss . *2 : i out depends on the output load conditions. *3 : the i cc current listed includes both the dc operating current and the frequency dependent component. *4 : i cc active while embedded algorithm (program or erase) is in progress. *5 : embedded algorithm (program or erase) is in progress. (@5 mhz) *6 : automatic sleep mode enables the low power mode when address remain stable for t acc + 60 ns. parameter symbol test conditions value unit min typ max input leakage current i li v in = v ss to v cc f, v cc sC1.0+1.0 m a output leakage current i lo v out = v ss to v cc f, v cc sC1.0+1.0 m a flash v cc active read current * 3 i cc1 fce f = v il , oe = v ih , we f = v ih 5 mhz 12 16 ma 1 mhz 3.3 5 flash v cc active write current * 4 i cc2 fce f = v il , oe = v ih , v pp = v ih 1540ma flash v cc active current (read-while-program)* 5 i cc3 fce f = v il , oe = v ih 2560ma flash v cc active current (read-while-erase)* 5 i cc4 fce f = v il , oe = v ih 2560ma sram v cc active current i cc1 s v cc s = v cc s max, ce 1s = v il , ce2s = v ih t cycle =10 mhz 50 ma sram v cc active current i cc2 s ce 1s = 0.2 v, ce2s = v cc s C 0.2 v t cycle = 10 mhz 50 ma t cycle = 1 mhz 10 ma flash v cc standby current i sb1 f v cc f = v cc f max, ce f = reset = v cc 0.2 v, v in < 0.2 v 0.210a flash v cc standby current (standby, reset ) * 6 i sb2 fv cc f = v cc f max, reset = v il 0.210a sram v cc standby current i sb1 sce 1s > v cc s C 0.2 v, ce2s > v cc s C 0.2 v 14 m a sram v cc standby current i sb2 sce2s < 0.2 v 14 m a input low level v il C0.20.2v input high level v ih flash v cc fC0.2 v cc f+0.2 v sram 1.6 v cc s+0.2 flash output low level v ol flash v cc f = v cc f min, i ol = 1.0 ma 0.1 v sram output low level sram v cc s = v cc s min, i ol = 2.1 ma 0.4 v flash output high level v oh flash v cc f = v cc f min, i oh = C0.1 ma v cc fC0.1 v sram output high level sram v cc s = v cc s min, i oh = C0.5 ma v cc sC0.5 v flash low v cc lock-out voltage v lko 1.0 1.4 v
mb84sd23280fa/mb84sd23280fe -70 8 n n n n ac characteristics ce timing timing diagram for alternating sram to flash parameter symbol condition value unit jedec standard min ce recover time t ccr 0 ce hold time t chold 3 ce f t ccr t ccr ce 1s ce2s t ccr t ccr we t chold t chold
mb84sd23280fa/mb84sd23280fe -70 9 n sector lock/unlock command the sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. when the device is first powered up, all sectors are locked. to unlock a sector, the system must write the sector lock/unlock command sequence. two cycles are first written: addresses are dont care and data is 60h. during the third cycle, the sector address (sla) and unlock command (60h) is written, while specifying with address a 6 whether that sector should be locked (a 6 = v il ) or unlocked (a 6 = v ih ). after the third cycle, the system can continue to lock or unlock additional cycles, or exit the sequence by writing f0h (reset command). ? flash characteristics please refer to n 64m flash memory for mcp 1.8 v. ? sram characteristics please refer to n 8m sram for mcp 1.8 v.
mb84sd23280fa/mb84sd23280fe -70 10 n n n n 64m flash memory for mcp 1.8 v 1. flexible sector-erase architecture on flash memory ? sixteen 4k words, and one hundred twenty-six 32k words. ? individual-sector, multiple-sector, or bulk-erase capability. sector architecture sa5 : 64kb sa6 : 64kb sa7 : 64kb sa8 : 64kb sa0 : 16kb sa1 : 16kb sa2 : 16kb sa3 : 16kb sa4 : 64kb sa9 : 64kb sa10 : 64kb sa11 : 64kb sa12 : 64kb sa13 : 64kb sa14 : 64kb sa15 : 64kb sa16 : 64kb sa17 : 64kb sa18 : 64kb sa19 : 64kb sa20 : 64kb sa21 : 64kb sa22 : 64kb sa23 : 64kb sa24 : 64kb sa25 : 64kb sa26 : 64kb sa27 : 64kb sa28 : 64kb sa29 : 64kb sa30 : 64kb sa31 : 64kb sa32 : 64kb sa33 : 64kb sa34 : 64kb sa35 : 64kb sa36 : 64kb sa37 : 64kb sa38 : 64kb sa39 : 64kb sa40 : 64kb sa41 : 64kb sa42 : 64kb sa43 : 64kb sa44 : 64kb sa45 : 64kb sa46 : 64kb sa47 : 64kb sa48 : 64kb sa49 : 64kb sa50 : 64kb sa51 : 64kb sa52 : 64kb sa53 : 64kb sa54 : 64kb sa55 : 64kb sa56 : 64kb sa57 : 64kb sa58 : 64kb sa59 : 64kb sa60 : 64kb sa61 : 64kb sa62 : 64kb sa63 : 64kb sa64 : 64kb sa65 : 64kb sa66 : 64kb sa71 : 64kb sa72 : 64kb sa73 : 64kb sa74 : 64kb sa67 : 64kb sa68 : 64kb sa69 : 64kb sa70 : 64kb sa75 : 64kb sa76 : 64kb sa77 : 64kb sa78 : 64kb sa79 : 64kb sa80 : 64kb sa81 : 64kb sa82 : 64kb sa83 : 64kb sa84 : 64kb sa85 : 64kb sa86 : 64kb sa87 : 64kb sa88 : 64kb sa89 : 64kb sa90 : 64kb sa91 : 64kb sa92 : 64kb sa93 : 64kb sa94 : 64kb sa95 : 64kb sa96 : 64kb sa97 : 64kb sa98 : 64kb sa99 : 64kb sa100: 64kb sa101: 64kb sa102: 64kb sa103: 64kb sa104: 64kb sa105: 64kb sa106: 64kb sa107: 64kb sa108: 64kb sa109: 64kb sa110: 64kb sa111: 64kb sa112: 64kb sa113: 64kb sa114: 64kb sa115: 64kb sa116: 64kb sa117: 64kb sa118: 64kb sa119: 64kb sa120: 64kb sa121: 64kb sa122: 64kb sa123: 64kb sa124: 64kb sa125: 64kb sa126: 64kb sa127: 64kb sa128: 64kb sa129: 64kb sa130: 16kb sa131: 16kb sa132: 16kb sa133: 16kb 000000h 002000h 004000h 006000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0a0000h 0a8000h 0b0000h 0b8000h 0c0000h 0c8000h 0d0000h 0d8000h 0e0000h 0e8000h 0f0000h 0f8000h 108000h 100000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1a0000h 1a8000h 1b0000h 1b8000h 1c0000h 1c8000h 1d0000h 1d8000h 1e0000h 1e8000h 1f0000h 1f8000h 1fffffh 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2a0000h 2a8000h 2b0000h 2b8000h 2c0000h 2c8000h 2d0000h 2d8000h 2e0000h 2e8000h 2f0000h 2f8000h 308000h 300000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3a0000h 3a8000h 3b0000h 3b8000h 3c0000h 3c8000h 3d0000h 3d8000h 3e0000h 3e8000h 3f0000h 3f8000h 3fa000h 3fc000h 3fe000h 3fffffh bank d bank c bank b bank a
mb84sd23280fa/mb84sd23280fe -70 11 ? flexbank tm architecture ? simultaneous operation * : by writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. note: bank 1 and bank 2 are divided for the sake of convenience at simultaneous operation. actually, the bank consists of 4 banks, bank a, bank b, bank c and bank d. bank address (ba) meant to specify each of the banks. bank quantity size a 48k words 31 32k words b 32 32k words c 32 32k words d 31 32k words 48k words case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
mb84sd23280fa/mb84sd23280fe -70 12 (continued) ? sector address table bank sector sector size ( 16) address range bank d sa0 8 kwords 000000h to 001fffh sa1 8 kwords 002000h to 003fffh sa2 8 kwords 004000h to 005fffh sa3 8 kwords 006000h to 007fffh sa4 32 kwords 008000h to 00ffffh sa5 32 kwords 010000h to 017fffh sa6 32 kwords 018000h to 01ffffh sa7 32 kwords 020000h to 027fffh sa8 32 kwords 028000h to 02ffffh sa9 32 kwords 030000h to 037fffh sa10 32 kwords 038000h to 03ffffh sa11 32 kwords 040000h to 047fffh sa12 32 kwords 048000h to 04ffffh sa13 32 kwords 050000h to 057fffh sa14 32 kwords 058000h to 05ffffh sa15 32 kwords 060000h to 067fffh sa16 32 kwords 068000h to 06ffffh sa17 32 kwords 070000h to 077fffh sa18 32 kwords 078000h to 07ffffh sa19 32 kwords 080000h to 087fffh sa20 32 kwords 088000h to 08ffffh sa21 32 kwords 090000h to 097fffh sa22 32 kwords 098000h to 09ffffh sa23 32 kwords 0a0000h to 0a7fffh sa24 32 kwords 0a8000h to 0affffh sa25 32 kwords 0b0000h to 0b7fffh sa26 32 kwords 0b8000h to 0bffffh sa27 32 kwords 0c0000h to 0c7fffh sa28 32 kwords 0c8000h to 0cffffh sa29 32 kwords 0d0000h to 0d7fffh sa30 32 kwords 0d8000h to 0dffffh sa31 32 kwords 0e0000h to 0e7fffh sa32 32 kwords 0e8000h to 0effffh sa33 32 kwords 0f0000h to 0f7fffh sa34 32 kwords 0f8000h to 0fffffh
mb84sd23280fa/mb84sd23280fe -70 13 (continued) bank sector sector size ( 16) address range bank c sa35 32 kwords 100000h to 107fffh sa36 32 kwords 108000h to 10ffffh sa37 32 kwords 110000h to 117fffh sa38 32 kwords 118000h to 11ffffh sa39 32 kwords 120000h to 127fffh sa40 32 kwords 128000h to 12ffffh sa41 32 kwords 130000h to 137fffh sa42 32 kwords 138000h to 13ffffh sa43 32 kwords 140000h to 147fffh sa44 32 kwords 148000h to 14ffffh sa45 32 kwords 150000h to 157fffh sa46 32 kwords 158000h to 15ffffh sa47 32 kwords 160000h to 167fffh sa48 32 kwords 168000h to 16ffffh sa49 32 kwords 170000h to 177fffh sa50 32 kwords 178000h to 17ffffh sa51 32 kwords 180000h to 187fffh sa52 32 kwords 188000h to 18ffffh sa53 32 kwords 190000h to 197fffh sa54 32 kwords 198000h to 19ffffh sa55 32 kwords 1a0000h to 1a7fffh sa56 32 kwords 1a8000h to 1affffh sa57 32 kwords 1b0000h to 1b7fffh sa58 32 kwords 1b8000h to 1bffffh sa59 32 kwords 1c0000h to 1c7fffh sa60 32 kwords 1c8000h to 1cffffh sa61 32 kwords 1d0000h to 1d7fffh sa62 32 kwords 1d8000h to 1dffffh sa63 32 kwords 1e0000h to 1e7fffh sa64 32 kwords 1e8000h to 1effffh sa65 32 kwords 1f0000h to 1f7fffh sa66 32 kwords 1f8000h to 1fffffh
mb84sd23280fa/mb84sd23280fe -70 14 (continued) bank sector sector size ( 16) address range bank b sa67 32 kwords 200000h to 207fffh sa68 32 kwords 208000h to 20ffffh sa69 32 kwords 210000h to 217fffh sa70 32 kwords 218000h to 21ffffh sa71 32 kwords 220000h to 227fffh sa72 32 kwords 228000h to 22ffffh sa73 32 kwords 230000h to 237fffh sa74 32 kwords 238000h to 23ffffh sa75 32 kwords 240000h to 247fffh sa76 32 kwords 248000h to 24ffffh sa77 32 kwords 250000h to 257fffh sa78 32 kwords 258000h to 25ffffh sa79 32 kwords 260000h to 267fffh sa80 32 kwords 268000h to 26ffffh sa81 32 kwords 270000h to 277fffh sa82 32 kwords 278000h to 27ffffh sa83 32 kwords 280000h to 287fffh sa84 32 kwords 288000h to 28ffffh sa85 32 kwords 290000h to 297fffh sa86 32 kwords 298000h to 29ffffh sa87 32 kwords 2a0000h to 2a7fffh sa88 32 kwords 2a8000h to 2affffh sa89 32 kwords 2b0000h to 2b7fffh sa90 32 kwords 2b8000h to 2bffffh sa91 32 kwords 2c0000h to 2c7fffh sa92 32 kwords 2c8000h to 2cffffh sa93 32 kwords 2d0000h to 2d7fffh sa94 32 kwords 2d8000h to 2dffffh sa95 32 kwords 2e0000h to 2e7fffh sa96 32 kwords 2e8000h to 2effffh sa97 32 kwords 2f0000h to 2f7fffh sa98 32 kwords 2f8000h to 2fffffh
mb84sd23280fa/mb84sd23280fe -70 15 (continued) bank sector sector size ( 16) address range bank a sa99 32 kwords 300000h to 307fffh sa100 32 kwords 308000h to 30ffffh sa101 32 kwords 310000h to 317fffh sa102 32 kwords 318000h to 31ffffh sa103 32 kwords 320000h to 327fffh sa104 32 kwords 328000h to 32ffffh sa105 32 kwords 330000h to 337fffh sa106 32 kwords 338000h to 33ffffh sa107 32 kwords 340000h to 347fffh sa108 32 kwords 348000h to 34ffffh sa109 32 kwords 350000h to 357fffh sa110 32 kwords 358000h to 35ffffh sa111 32 kwords 360000h to 367fffh sa112 32 kwords 368000h to 36ffffh sa113 32 kwords 370000h to 377fffh sa114 32 kwords 378000h to 37ffffh sa115 32 kwords 380000h to 387fffh sa116 32 kwords 388000h to 38ffffh sa117 32 kwords 390000h to 397fffh sa118 32 kwords 398000h to 39ffffh sa119 32 kwords 3a0000h to 3a7fffh sa120 32 kwords 3a8000h to 3affffh sa121 32 kwords 3b0000h to 3b7fffh sa122 32 kwords 3b8000h to 3bffffh sa123 32 kwords 3c0000h to 3c7fffh sa124 32 kwords 3c8000h to 3cffffh sa125 32 kwords 3d0000h to 3d7fffh sa126 32 kwords 3d8000h to 3dffffh sa127 32 kwords 3e0000h to 3e7fffh sa128 32 kwords 3e8000h to 3effffh sa129 32 kwords 3f0000h to 3f7fffh sa130 8 kwords 3f8000h to 3f9fffh sa131 8 kwords 3fa000h to 3fbfffh sa132 8 kwords 3fc000h to 3fdfffh sa133 8 kwords 3fe000h to 3fffffh
mb84sd23280fa/mb84sd23280fe -70 16 ? sector protection verify autoselect codes table legend: l = v i l , h = v i h . see n dc characteristics for voltage levels. *1: a read cycle at address (ba) 01h outputs device code. when 227eh is output, it indicates that two additional codes, called extended device codes, will be required. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh, as well as at (ba) 0fh *2: outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. type a 21 to a 13 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 code (hex) manufactures code ba* 2 llllllll 04h device code ba* 2 l l l l l l l h 227eh extended device code* 1 ba l l l l h h h l 2224h ba l l l l h h h h 2201h sector lock/ unlock sector addresses llllllhl 01h* 2
mb84sd23280fa/mb84sd23280fe -70 17 ? flash memory command definitions legend: ra = address of the memory location to be read. pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , and a 14 will uniquely select any sector. ba = bank address. address setted by a 22 , a 21 will select bank a, bank b, bank c and bank d. sla = address of the sector to be locked. set sector address (sa) and either a 6 = 1 for unlocked or a 6 = 0 for locked. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data latches on the rising edge of write pulse. cr = configuration register address bits a 19 to a 12 . *1: this command is valid during fast mode. *2: the data 00h is also acceptable. notes: address bits a 21 to a 11 = x = h or l for all address commands except for pa, sa, ba. bus operations are defined in n device bus operation. both read/reset commands are functionally equivalent, resetting the device to the read mode. command sequence bus write cycles reqd first bus write cycle second write cycle third write cycle fourth write cycle fifth write cycle sixth write cycle addr. data addr. data addr. data addr. data addr. data addr. data read / reset 1 xxxh f0h ra rd read / reset 3 555h aah 2aah 55h 555h f0h ra rd autoselect 3 555h aah 2aah 55h (ba) 555h 90h program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h erase suspend 1 bab0h erase resume 1 ba30h fast program 2 xxxh a0 pa pd set to fast mode 3 555haah2aah55h555h20h reset from fast mode * 1 2 ba 90h xxxh f0h* 2 sector lock/unlock 3 xxxh 60h xxxh 60h sla 60h query 1 (ba) 55h 98h
mb84sd23280fa/mb84sd23280fe -70 18 2. ac characteristics ? read operations *1 : access time is from the last of either stable addresses. *2 : not 100% tested. ? hardware reset (reset ) * : not 100% tested. parameter symbol value unit jedec standard min max access time from ce f low t ce ? 70 ns access time * 1 t acc ? 70 ns output enable to output valid t oe ? 20 ns output enable hold time read t oeh 0 ? ns toggle and data polling 10 ? ns output enable to high-z * 2 t oez ? 10 ns parameter symbol value unit jedec standard min max reset pin low (during embedded algorithms) to read mode* t ready ? 20 s reset pin low (not during embedded algorithms) to read mode* t ready ? 500 ns reset pulse width t rp 500 ? ns reset high time before read* t rh 200 ? ns reset low to standby mode t rpd 20 ? s
mb84sd23280fa/mb84sd23280fe -70 19 ? erase/program operations *1 : not 100% tested. *2 : addresses are latched on the falling edge of we . *3 : see the erase and programming performance section in bds64xf datasheet for more information. *4 : does not include the preprogramming time. parameter symbol value unit jedec standard min typ max write cycle time* 1 t avav t wc 80 ?? ns address setup time* 2 t avwl t as 0 ?? ns address hold time* 2 t wlax t ah 45 ?? ns data setup time t dvwh t ds 45 ?? ns data hold time t whdx t dh 0 ?? ns read recovery time before write t ghwl t ghwl 0 ?? ns ce hold time t wheh t ch 0 ?? ns write pulse width t ehwh t wp 50 ?? ns write pulse width high t whwl t wph 30 ?? ns latency between read and write operations t sr/w 0 ?? ns programming operation* 3 t whwh1 t whwh1 ? 8 ? s sector erase operation* 3, * 4 t whwh2 t whwh2 ? 0.5 ? s chip erase operation* 3, * 4 ? 67.0 ? v cc setup time t vcs 50 ?? s ce setup time to we t elwl t cs 0 ?? ns
mb84sd23280fa/mb84sd23280fe -70 20 3. erase and programming performance note: typical erase conditions: t a = + 25c, v cc f = 1.8 v typical program conditions: t a = + 25c, v cc f = 1.8 v, data = checker parameter value unit comments min typ max sector erase time 0.5 2.0 s excludes programming prior to erasure word programming time 6 100 s excludes system level overhead chip programming time 25.2 95 s excludes system level overhead erase/program cycle 100,000 cycle
mb84sd23280fa/mb84sd23280fe -70 21 ? read mode ? reset timings note: ra = read address, rd = read data. t ce we a 21 to a 0 cef oe valid rd t acc t oeh t oe dq 15 to dq 0 t oez ra t cas reset t rp t ready reset timings not during embedded algorithms t ready cef, oe t rh cef, oe reset timings during embedded algorithms reset t rp
mb84sd23280fa/mb84sd23280fe -70 22 ? program operation timings notes : pa = program address, pd = program data, va = valid address for reading status bits. in progress and complete refer to status of program operation in mbm29bs64lf data sheet. a 21 to a 12 are dont care during command sequence unlock cycles. oe cef data address we v cc f 555h pd t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds a0h t cs
mb84sd23280fa/mb84sd23280fe -70 23 ? chip/sector erase command sequence notes : sa is the sector address for sector erase. address bits a 21 to a 12 are dont cares during unlock cycles in the command sequence. oe cef data address we v cc f t wp t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase 555h/55h 2aah 10h/30h
mb84sd23280fa/mb84sd23280fe -70 24 ?data polling timings (during embedded algorithm) note : va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data polling will output true data. we cef oe t oe address t oeh t ce t ch t oez t cez status data status data t acc va va
mb84sd23280fa/mb84sd23280fe -70 25 ? toggle bit timings (during embedded algorithm) note : va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. we cef oe t oe address t oeh t ce t ch t oez t cez status data status data t acc va va
mb84sd23280fa/mb84sd23280fe -70 26 ? bank-to-bank read/write cycle timings note: break points in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the program or erase operation in the busy bank. the system should read status twice to ensure valid information. oe cef we t oeh data address pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph
mb84sd23280fa/mb84sd23280fe -70 27 n n n n 8m sram for mcp 1.8 v 1. ac characteristics ?read cycle (sram) note: test conditionsCoutput load:1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 1.8 v timing measurement reference level input: 0.5 v cc s output: 0.5 v cc s parameter symbol value unit min max read cycle time t rc 70 ns address access time t aa 70ns chip enable (ce 1s) access time t co1 70ns chip enable (ce2s) access time t co2 70ns output enable access time t oe 35ns lb , ub to output valid t ba 70ns chip enable (ce 1s low and ce2s high) to output active t coe 5ns output enable low to output active t oee 0ns lb , ub enable low to output active t be 5ns chip enable (ce 1s high or ce2s low) to output high-z t od 25ns output enable high to output high-z t odo 25ns lb , ub output enable to output high-z t bd 25ns output data hold time t oh 5ns
mb84sd23280fa/mb84sd23280fe -70 28 ?read cycle (sram) t rc t aa t oh t co1 t od t odo t oee t coe valid data output address ce 1s oe dq ce2s t coe t oe t co2 t od lb , ub t ba t bd t be note: we remains high for the read cycle.
mb84sd23280fa/mb84sd23280fe -70 29 ? write cycle (sram) parameter symbol value unit min max write cycle time t wc 70 ns write pulse width t wp 55 ns ce 1s to end of write t cw1 55 ns ce2s to end of write t cw2 55 ns address valid to end of write t aw 55 ns lb , ub to end of write t bw 55 ns address setup time t as 0ns write recovery time t wr 0ns we low to output high-z t odw 25ns we high to output active t oew 0ns data setup time t ds 30 ns data hold time t dh 0ns
mb84sd23280fa/mb84sd23280fe -70 30 ?write cycle* 1 (we control) (sram) *1 : if oe is high during the write cycle, the outputs will remain at high impedance. *2 : if ce 1s goes low (or ce2s goes high) coincident with or after we goes low, the output will remain at high impedance. *3 : if ce 1s goes high (or ce2s goes low) coincident with or before we goes high, the output will remain at high impedance. *4 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wc t as t wp t wr t cw t odw t oew t ds t dh valid data input address we ce 1s d out d in ce2s t cw *2 *4 *3 *4 t bw lb , ub t aw
mb84sd23280fa/mb84sd23280fe -70 31 ?write cycle* 1 (ce 1 s control) (sram) *1: if oe is high during the write cycle, the outputs will remain at high impedance. *2: because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wc t as t wp t wr t cw t odw t coe t ds t dh valid data input address we ce 1s d out d in ce2s t cw *2 *2 lb , ub t bw t be t aw
mb84sd23280fa/mb84sd23280fe -70 32 ?write cycle* 1 (ce2s control) (sram) *1 : if oe is high during the write cycle, the outputs will remain at high impedance. *2 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wc t as t wp t wr t cw t odw t coe t ds t dh valid data input address we ce 1s d out d in ce2s *2 *2 t cw lb , ub t bw t be t aw
mb84sd23280fa/mb84sd23280fe -70 33 ?write cycle* 1 (lb , ub control) (sram) *1 : if oe is high during the write cycle, the outputs will remain at high impedance. *2 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wc t ds t dh address lb , ub we d in t wp ce2s t cw ce 1s t as t wr t bw t odw t coe d out t be valid data input *2 *2 t cw t aw
mb84sd23280fa/mb84sd23280fe -70 34 2. data retention characteristics (sram) note : t rc : read cycle time ?ce 1s controlled data retention mode * 1 *1 : in ce 1s controlled data retention mode, input level of ce2s should be fixed vccs to v cc sC0.2 v or v ss to 0.2 v during data retention mode. other input and input/output pins can be used between C0.3 v to v cc s+0.3 v. *2 : when ce 1s is operating at the v ih min level, the standby current is given by i sb1 s during the transition of v cc s from vccs max to v ih min level. parameter symbol value unit min typ max data retention supply voltage v dh 1.0 1.95 v standby current v dh = 1.8 v i dds2 0.314 m a chip deselect to data retention mode time t cdr 0ns recovery time t r t rc ns v cc s 1.65 v v ih v ss data retention mode *2 t cdr ce 1s v ccs C 0.2 v *2 t r v dh
mb84sd23280fa/mb84sd23280fe -70 35 ? ce2s controlled data retention mode* * : in ce2s controlled data retention mode, input and input/output pins can be used between C0.3 v to vccs+0.3 v. v cc s 1.65 v v ss data retention mode v ih v il ce2s t cdr t r 0.2 v v dh
mb84sd23280fa/mb84sd23280fe -70 36 n pin capacitance note : test conditions t a = + 25 c, f = 1.0 mhz n n n n handling of package please handle this package carefully since the sides of package create acute angles. n n n n caution the high voltage (v id ) cannot apply to address pins and control pins. parameter symbol test setup value unit min typ max input capacitance c in v in = 0 16.0 pf output capacitance c out v out = 0 22.0 pf control pin capacitance c in2 v in = 0 18.0 pf
mb84sd23280fa/mb84sd23280fe -70 37 n n n n ordering information mb84sd23280 fa/e -70 pbs device number/description 64 mega-bit (4 m 16-bit) dual operation flash memory 1.8 v-only read, program, and erase 8 mega-bit (512k 16-bit) sram pa c k a g e t y p e pbs = 73-ball fbga speed option device revision
mb84sd23280fa/mb84sd23280fe -70 38 n n n n package dimension 73-ball plastic fbga (bga-73p-m03) dimensions in mm (inches) . note : the values in parentheses are reference values. c 2003 fujitsu limited b73003s-c-1-1 11.60 0.10(.457 .004) .047 C.004 +.006 C0.10 +0.15 1.19 (seated height) 0.39 0.10 (.015 .004) (stand off) 1 2 3 4 5 6 7 8 9 10 a b c d e f g h index ball 73- ? 0.18 C.002 +.004 C.005 +0.10 73- ? 0.45 index-mark area 8.00 0.10 (.315 .004) j k l m a s 0.20(.008) ref 0.80(.031) b ref 0.40(.016) ref 0.80(.031) a ref 0.40(.016) s 0.10(.004) s ab s m ? 0.08(.003) 0.20(.008) s b 0.10(.004) s
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